View AD82504_4139679.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Low Cost, General-Purpose High Speed JFET Amplifier AD825
FEATURES
High speed 41 MHz, -3 dB bandwidth 125 V/s slew rate 80 ns settling time Input bias current of 20 pA and noise current of 10 fA/Hz Input voltage noise of 12 nV/Hz Fully specified power supplies: 5 V to 15 V Low distortion: -76 dB at 1 MHz High output drive capability Drives unlimited capacitance load 50 mA min output current No phase reversal when input is at rail Available in 8-lead SOIC
CONNECTION DIAGRAMS
NC 1 -IN 2
8
NC
NC = NO CONNECT
Figure 1. 8-Lead Plastic SOIC (R) Package
NC 1 NC 2 NC 3 -INPUT 4
16 NC 15 NC 14 NC
13 +VS TOP VIEW +INPUT 5 (Not to Scale) 12 OUTPUT 11 NC -VS 6
AD825
CCDs Low distortion filters Mixed gain stages Audio amplifiers Photo detector interfaces ADC input buffers DAC output buffers
NC 8
9
NC
NC = NO CONNECT
Figure 2. 16-Lead Plastic SOIC (R-16) Package
GENERAL DESCRIPTION
The AD825 is a superbly optimized operational amplifier for high speed, low cost, and dc parameters, making it ideally suited for a broad range of signal conditioning and data acquisition applications. The ac performance, gain, bandwidth, slew rate, and drive capability are all very stable over temperature. The AD825 also maintains stable gain under varying load conditions. The unique input stage has ultralow input bias current and input current noise. Signals that go to either rail on this high performance input do not cause phase reversals at the output. These features make the AD825 a good choice as a buffer for MUX outputs, creating minimal offset and gain errors. The AD825 is fully specified for operation with dual 5 V and 15 V supplies. This power supply flexibility, and the low supply current of 6.5 mA with excellent ac characteristics under all supply conditions, makes the AD825 well-suited for many demanding applications.
10V 200ns
00876-E-002
APPLICATIONS
NC 7
10 NC
00876-E-001
+VS TOP VIEW 6 OUTPUT (Not to Scale) -VS 4 5 NC
7
AD825
+IN 3
10V
Figure 3. Performance with Rail-to-Rail Input Signals
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
00876-E-003
AD825 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Pin Configurations ........................................................................... 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Driving Capacitive Loads .............................................................. 10 Theory of Operation ...................................................................... 10 Input Consideration................................................................... 10 Grounding and Bypassing ......................................................... 10 Second-Order Low-Pass Filter.................................................. 11 Outline Dimensions ....................................................................... 12 Ordering Guide........................................................................... 12
REVISION HISTORY
10/04--Data Sheet Changed from Rev. E to Rev. F Changes to Figure 1......................................................................... 1 Changes to Figure 4......................................................................... 5 Changes to Figure 21....................................................................... 8 3/04--Data Sheet Changed from Rev. D to Rev. E Changes to Specifications............................................................... 3 Addition of 16-Lead SOIC Pin Configuration ............................ 5 Changes to Figure 27....................................................................... 9 Updated Outline Dimensions...................................................... 12 Updated Ordering Guide.............................................................. 12 2/01--Data Sheet Changed from Rev. C to Rev. D Addition of 16-lead SOIC package (R-16) Connection Diagram ...................................................................... 4 Addition to Absolute Maximum Ratings ..................................... 4 Addition to Ordering Guide (R-16).............................................. 4 Addition of 16-lead SOIC package (R-16) Outline Dimensions ...................................................................... 11
Rev. F | Page 2 of 12
AD825 SPECIFICATIONS
All limits are determined to be at least four standard deviations away from mean value. At TA = 25C, VS = 15 V, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Unity Gain Bandwidth Bandwidth for 0.1 dB Flatness -3 dB Bandwidth Slew Rate Settling Time to 0.1% to 0.1% Total Harmonic Distortion Differential Gain Error (RLOAD = 150 ) Differential Phase Error (RLOAD = 150 ) INPUT OFFSET VOLTAGE Offset Drift INPUT BIAS CURRENT TMIN TMAX INPUT OFFSET CURRENT TMIN TMAX VOUT = 10 V RLOAD = 1 k VOUT = 7.5 V RLOAD = 1 k VOUT = 7.5 V RLOAD = 150 k (50 mA Output) VCM = 10 f = 10 kHz f = 10 kHz RLOAD = 1 k RLOAD = 500 15 V 5 440 15 V 70 15 V 70 15 V 15 V 15 V 15 V 15 V 15 V 15 V 15 V 15 V 13 12.9 50 68 71 74 80 12 10 13.5 13.3 13.2 100 5 x1011 6 8 6.5 7.2 7.5 dB dB nV/Hz fA/Hz V V V mA mA pF mA mA 76 dB 76 dB Conditions VS 15 V 15 V 15 V 15 V 15 V 15 V 15 V 15 V 15 V 15 V TMIN to TMAX 15 V 5 20 700 30 10 15 Min 23 18 44 125 AD825A Typ 26 21 46 140 150 180 -77 1.3 2.1 1 2 5 40 Max Unit MHz MHz MHz V/s ns ns dB % Degrees mV mV V/C pA pA pA pA pA pA
Gain = +1 Gain = +1 RLOAD = 1 k, G = +1 0 V to 10 V Step, AV = -1 0 V to 10 V Step, AV = -1 FC = 1 MHz, G = -1 NTSC Gain = +2 NTSC Gain = +2
180 220
OPEN-LOOP GAIN
COMMON-MODE REJECTION INPUT VOLTAGE NOISE INPUT CURRENT NOISE INPUT COMMON-MODE VOLTAGE RANGE OUTPUT VOLTAGE SWING Output Current Short-Circuit Current INPUT RESISTANCE INPUT CAPACITANCE OUTPUT RESISTANCE POWER SUPPLY Quiescent Current
Open Loop 15 V 15 V
TMIN to TMAX
Rev. F | Page 3 of 12
AD825
All limits are determined to be at least four standard deviations away from mean value. At TA = 25C, VS = 5 V unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE Unity Gain Bandwidth Bandwidth for 0.1 dB Flatness -3 dB Bandwidth Slew Rate Settling Time to 0.1% to 0.01% Total Harmonic Distortion Differential Gain Error (RLOAD = 150 ) Differential Phase Error (RLOAD = 150 ) INPUT OFFSET VOLTAGE Offset Drift INPUT BIAS CURRENT TMIN TMAX INPUT OFFSET CURRENT Offset Current Drift OPEN-LOOP GAIN TMIN TMAX VOUT = 2.5 RLOAD = 500 RLOAD = 150 VCM = 2 V f = 10 kHz f = 10 kHz RLOAD = 500 RLOAD = 150 5 V 5 280 5 V 64 64 69 66 66 80 12 10 +3.2 +3.1 50 3.5 3.4 3.2 80 5 x1011 6 8 5 V 5 V 76 6.2 88 6.8 7.5 dB dB dB nV/Hz fA/Hz V V V mA mA pF mA mA dB Conditions VS 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V TMIN to TMAX 5 V 5 15 600 25 10 10 Min 18 8 34 115 AD825A Typ 21 10 37 130 75 90 -76 1.2 1.4 1 2 5 30 Max Unit MHz MHz MHz V/s ns ns dB % Degrees mV mV V/C pA pA pA pA pA pA
Gain = +1 Gain = +1 RLOAD = 1 k, G = -1 -2.5 V to +2.5 V -2.5 V to +2.5 V FC = 1 MHz, G = -1 NTSC Gain = +2 NTSC Gain = +2
90 110
COMMON-MODE REJECTION INPUT VOLTAGE NOISE INPUT CURRENT NOISE INPUT COMMON-MODE VOLTAGE RANGE OUTPUT VOLTAGE SWING Output Current Short-Circuit Current INPUT RESISTANCE INPUT CAPACITANCE OUTPUT RESISTANCE POWER SUPPLY Quiescent Current POWER SUPPLY REJECTION
5 V 5 V 5 V 5 V 5 V 5 V
Open Loop
TMIN to TMAX VS = 5 V to 15 V
Rev. F | Page 4 of 12
AD825 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Internal Power Dissipation1 Small Outline (R) Input Voltage (Common Mode) Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range (R, R-16) Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Rating 18 V See Figure 6 VS VS See Figure 6 -65C to +125C -40C to +85C 300C
PIN CONFIGURATIONS
NC 1 -IN 2
8
NC
NC = NO CONNECT
Figure 4. 8-Lead SOIC
NC 1 NC 2 NC 3 -INPUT 4
16 15 14
NC NC NC
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.5
+VS TOP VIEW +INPUT 5 (Not to Scale) 12 OUTPUT 11 NC -VS 6
13
AD825
NC 7 NC 8
10 9
NC NC
00876-E-002
NC = NO CONNECT
Figure 5. 16-Lead SOIC
1
Specification is for device in free air: 8-lead SOIC package: JA = 155C/W 16-lead SOIC package: JA = 85C/W
MAXIMUM POWER DISSIPATION (W)
2.0
16-LEAD SOIC PACKAGE
1.5
1.0
0.5
8-LEAD SOIC PACKAGE
00876-E-001
+VS TOP VIEW 6 OUTPUT (Not to Scale) -VS 4 5 NC
7
AD825
+IN 3
TJ = 150C
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE (C)
Figure 6. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. F | Page 5 of 12
00876-E-004
AD825 TYPICAL PERFORMANCE CHARACTERISTICS
20 15
OUTPUT IMPEDANCE ()
100
10
OUTPUT SWING (V)
10
5 RL = 150 0 -5 -10 -15
00876-E-005
RL = 1k
1
0.1
-20
0
2
4
6 8 10 12 SUPPLY VOLTAGE (V)
14
16
18
0.01 100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 7. Output Voltage Swing vs. Supply Voltage
15
35
Figure 10. Closed-Loop Output Impedance vs. Frequency
80 BANDWIDTH
VS = 15V
UNITY GAIN BANDWIDTH (MHz)
10
30 25
OUTPUT SWING (V)
5
60 20 PHASE MARGIN 15 40 10
0
VS = 5V
-5 VS = 15V -10
00876-E-006
5 0 -60 20 140
00876-E-009
-15
0
100
200
300 400 500 600 700 LOAD RESISTANCE ()
800
900
1000
-40
-20
0
60 20 40 80 TEMPERATURE (C)
100
120
Figure 8. Output Voltage Swing vs. Load Resistance
7.0 -40 +25
Figure 11. Unity Gain Bandwidth and Phase Margin vs. Temperature
80 VS = 15V 70 60 50 40 30 20 10
00876-E-007
180 135 VS = 5V 90 45 0
OPEN-LOOP PHASE (Degrees)
00876-E-010
SUPPLY CURRENT (mA)
+85
6.0
5.5
OPEN-LOOP GAIN (dB)
6.5
5.0
0
2
4
6
8 10 12 14 SUPPLY VOLTAGE (V)
16
18
20
0 1k
10k
100k 1M FREQUENCY (Hz)
10M
100M
Figure 9. Quiescent Supply Current vs. Supply Voltage for Various Temperatures
Figure 12. Open-Loop Gain and Phase Margin vs. Frequency
Rev. F | Page 6 of 12
PHASE MARGIN (C)
00876-E-008
AD825
80
30 RL = 1k
OPEN-LOOP GAIN (dB)
75 VS = 15V 70
OUTPUT VOLTAGE (V p-p)
20
RL = 150
VS = 5V 65
10
60 10
00876-E-011
1k LOAD RESISTANCE ()
10k
0 10k
100k
1M FREQUENCY (Hz)
10M
Figure 13. Open-Loop Gain vs. Load Resistance
10 0 -10 -PSRR
SETTLING TIME (ns)
200 180 160 140 120
Figure 16. Large Signal Frequency Response; G = +2
-20
PSR (dB)
-30 +PSRR -40 -50 -60 -70 -80
00876-E-012
0.01% 0.01%
100 0.1% 80 60 40 20 0 10 8 6 4 2 0 -2 -4 OUTPUT SWING (0 to V) -6 -8 -10
00876-E-015
0.1%
-90
10k
100k
1M FREQUENCY (Hz)
10M
Figure 14. Power Supply Rejection vs. Frequency
130 120 -55 110 100 VS = 15V -60 -50
Figure 17. Output Swing and Error vs. Settling Time
DISTORTION (dB)
SECOND -65 THIRD -70 -75 -80
CMR (dB)
90 80 70 60 50 40
00876-E-013
VS = 5V
00876-E-014
30 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
-85 100k
1M FREQUENCY (Hz)
10M
Figure 15. Common-Mode Rejection vs. Frequency
Figure 18. Harmonic Distortion vs. Frequency
Rev. F | Page 7 of 12
00876-E-016
AD825
160 15V 140 120 100 80 60 40 20 0 -60
00876-E-017
+VS
10F 0.01F
5V
2
7 6
SLEW RATE (V/s)
RL 10F
-VS
Figure 22. Noninverting Amplifier Connection
-40
-20
0
60 20 40 80 TEMPERATURE (C)
100
120
140
Figure 19. Slew Rate vs. Temperature
2 1 0 -1
5V
100ns
GAIN (dB)
-2 -3 -4 -5 -6 -7 -8 1k 10k 100k 1M 10M
00876-E-018
VIN VS 5V 10MHz 15V 21MHz
VOUT 0.1dB FLATNESS
5V
FREQUENCY (Hz)
Figure 20. Closed-Loop Gain vs. Frequency, Gain = +1
2
Figure 23. Noninverting Large Signal Pulse Response, RL = 1 k
200mV
1 0 -1
50ns
GAIN (dB)
-2 -3 -4 -5 -6 -7 -8 1k VS 0.1dB FLATNESS VIN 1k 1k
VOUT
200mV
100k 1M FREQUENCY (Hz) 10M
00876-E-019
10k
Figure 21. Closed-Loop Gain vs. Frequency, Gain = -1
Figure 24. Noninverting Small Signal Pulse Response, RL = 1 k
Rev. F | Page 8 of 12
00876-E-022
5V 7.7MHz 15V 9.8MHz
00876-E-021
00876-E-020
HP PULSE (LS) AD825 VIN OR 3 4 FUNCTION (SS) GENERATOR 50
VOUT
TEKTRONIX P6204 FET PROBE
TEKTRONIX 7A24 PREAMP
0.01F
AD825
5V 100ns 5V 100ns
00876-E-023
5V
5V
Figure 25. Noninverting Large Signal Pulse Response, RL = 150
Figure 28. Inverting Large Signal Pulse Response, RL = 1 k
200mV
50ns
200mV
50ns
00876-E-024
200mV
200mV
Figure 26. Noninverting Small Signal Pulse Response, RL = 150
1k +VS 10F 0.01F HP PULSE VIN GENERATOR RIN 1k
7 2
Figure 29. Inverting Small Signal Pulse Response, RL = 1 k
AD825
3 4
6
VOUT
TEKTRONIX P6204 FET PROBE RL
TEKTRONIX 7A24 PREAMP
00876-E-025
50 -VS
0.01F 10F
Figure 27. Inverting Amplifier Connection
Rev. F | Page 9 of 12
00876-E-027
00876-E-026
AD825 DRIVING CAPACITIVE LOADS
The internal compensation of the AD825, together with its high output current drive, permits excellent large signal performance while driving extremely high capacitive loads.
NEG VPOS
1k +VS 10F 0.01F HP PULSE VIN GENERATOR RIN 1k
7 2
POS
CF
VOUT
AD825
3 4
6
VOUT
TEKTRONIX P6204 FET PROBE CL
TEKTRONIX 7A24 PREAMP
00876-E-028
50 -VS
0.01F 10F
VNEG
Figure 30. Inverting Amplifier Driving a Capacitive Load Figure 32. Simplified Schematic
5V INPUT 500ns
The capacitor, CF, in the output stage, enables the AD825 to drive heavy capacitive loads. For light loads, the gain of the output buffer is close to unity, CF is bootstrapped, and not much happens. As the capacitive load is increased, the gain of the output buffer is decreased and the bandwidth of the amplifier is reduced through a portion of CF adding to the dominant pole. As the capacitive load is further increased, the amplifier's bandwidth continues to drop, maintaining the stability of the AD825.
00876-E-029
OUTPUT 5V
INPUT CONSIDERATION
The AD825 with its unique input stage ensures no phase reversal for signals as large as or even larger than the supply voltages. Also, layout considerations of the input transistors ensure functionality even with a large differential signal. The need for a low noise input stage calls for a larger FET transistor. One should consider the additional capacitance that is added to ensure stability. When filters are designed with the AD825, one needs to consider the input capacitance (5 pF to 6 pF) of the AD825 as part of the passive network.
Figure 31. Inverting Amplifier Pulse Response While Driving a 400 pF Capacitive Load
THEORY OF OPERATION
The AD825 is a low cost, wideband, high performance FET input operational amplifier. With its unique input stage design, the AD825 ensures no phase reversal, even for inputs that exceed the power supply voltages, and its output stage is designed to drive heavy capacitive or resistive loads with small changes relative to no load conditions. The AD825 (Figure 32) consists of common-drain, commonbase FET input stage driving a cascoded, common-base matched NPN gain stage. The output buffer stage uses emitter followers in a Class AB amplifier that can deliver large current to the load while maintaining low levels of distortion.
GROUNDING AND BYPASSING
The AD825 is a low input bias current FET amplifier. Its high frequency response makes it useful in applications, such as photodiode interfaces, filters, and audio circuits. When designing high frequency circuits, some special precautions are in order. Circuits must be built with short interconnects, and resistances should have low inductive paths to ground. Power supply leads should be bypassed to common as close as possible to the amplifier pins. Ceramic capacitors of 0.1 F are recommended.
Rev. F | Page 10 of 12
00876-E-030
AD825
SECOND-ORDER LOW-PASS FILTER
A second-order Butterworth low-pass filter can be implemented using the AD825 as shown in Figure 33. The extremely low bias currents of the AD825 allow the use of large resistor values and, consequently, small capacitor values without concern for developing large offset errors. Low current noise is another factor in permitting the use of large resistors without having to worry about the resultant voltage noise. With the values shown, the corner frequency will be 1 MHz. The equations for component selection are shown below. Note that the noninverting input (and the inverting input) has an input capacitance of 6 pF. As a result, the calculated value of C1 (12 pF) is reduced to 6 pF.
VIN R1 9.31k R2 9.31k C2 6pF C1 24pF +5V C3 0.1F
AD825
VOUT
-5V
Figure 33. Second-Order Butterworth Low-Pass Filter
0
HIGH FREQUENCY REJECTION (dB)
-10 -20 -30 -40 -50 -60 -70 -80
C1 =
1.414 2 f CUTOFF R1
0.707 C2 ( farads ) = 2 f CUTOFF R1 R1 = R2 = User Selected (Typically 10 k to 100 k ) A plot of the filter frequency response is shown in Figure 34; better than 40 dB of high frequency rejection is provided.
00876-E-031
C4 0.1F
10k
100k
1M FREQUENCY (Hz)
10M
100M
Figure 34. Frequency Response of Second-Order Butterworth Filter
Rev. F | Page 11 of 12
00876-E-032
AD825 OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
5.00 (0.1968) 4.80 (0.1890)
8 5 4
16
9
7.60 (0.2992) 7.40 (0.2913)
6.20 (0.2440) 5.80 (0.2284)
1 8
4.00 (0.1574) 3.80 (0.1497) 1
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) x 45 0.25 (0.0098)
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
SEATING PLANE
8 0.33 (0.0130) 0 0.20 (0.0079)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 35. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters (inches)
Figure 36. 16-Lead Standard Small Outline Package [SOIC] Wide Body (R-16) Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model AD825AR AD825AR-REEL AD825AR-REEL7 AD825AR-16 AD825AR-16-REEL AD825AR-16-REEL7 AD825ARZ-161 AD825ARZ-16-REEL1 AD825ARZ-16-REEL71 AD825ACHIPS Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead SOIC 8-Lead SOIC, 13" Tape and Reel 8-Lead SOIC, 7" Tape and Reel 16-Lead SOIC 16-Lead SOIC, 13" Tape and Reel 16-Lead SOIC, 7" Tape and Reel 16-Lead SOIC 16-Lead SOIC, 13" Tape and Reel 16-Lead SOIC, 7" Tape and Reel Die Package Option R-8 R-8 R-8 R-16 R-16 R-16 R-16 R-16 R-16
1
Z = Pb-free part.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00876-0-10/04(F)
Rev. F | Page 12 of 12

▲Up To Search▲

Price & Availability of AD82504

	To Download AD82504 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .